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4-bit single-chip microcontrollers for infrared remote control transmission description the m pd64a and 65 feature low-voltage 2.0 v operation, and incorporate a carrier generator for infrared remote control transmission, a standby release function through key entry, and a programmable timer, making them ideal for infrared remote control transmitters. a one-time prom product, the m pd6p5 is also available for program evaluation or small-quantity production. features ? program memory (rom) ? m pd64a: 1002 10 bits ? m pd65: 2026 10 bits ? data memory (ram): 32 4 bits ? on-chip carrier generator for infrared remote control ? 9-bit programmable timer: 1 channel ? instruction execution time: 16 m s (when operating at f x = 4 mhz: ceramic oscillation) ? stack levels: 1 (stack ram is also used for data memory rf) ? i/o pins (k i/o ): 8 ? input pins (k i ): 4 ? sense input pin (s 0 , s 2 ): 2 ?s 1 /led pin (i/o): 1 (when in output mode, this is the remote control transmission display pin.) ? power supply voltage: v dd = 2.0 to 3.6 v ? operating ambient temperature: t a = C40 to +85 c ? oscillation frequency: f x = 2.4 to 8 mhz ? on-chip poc circuit applications infrared remote control transmitters (for av and household electric appliances) unless otherwise specified, the m pd65 is treated as the representative model throughout this document. mos integrated circuit m pd64a, 65 document no. u14380ej3v0ds00 (3rd edition) date published december 2000 n cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. 1999 data sheet
2 m pd64a, 65 data sheet u14380ej3v0ds00 ordering information part number package m pd64amc- -5a4 20-pin plastic ssop (7.62 mm (300)) m pd65mc- -5a4 20-pin plastic ssop (7.62 mm (300)) remark indicates rom code suffix. pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) m pd64amc- -5a4 m pd65mc- -5a4 caution the pin numbers of k i and k i/o are in the reverse order of the m pd6600a and 6124a. 1 2 3 4 5 6 7 8 9 10 k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 20 19 18 17 16 15 14 13 12 11 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0
3 m pd64a, 65 data sheet u14380ej3v0ds00 block diagram list of functions item rom capacity 1002 10 bits mask rom one-time prom ram capacity 32 4 bits stack 1 level (multiplexed with rf of ram) i/o pins key input (k i ): 4 key i/o (k i/o ): 8 key extended input (s 0 , s 1 , s 2 ): 3 remote control transmission display output (led): 1 (alternate function as s 1 pin) number of keys 32 56 (when extended by key extension input) clock frequency ceramic oscillation ceramic oscillation f x = 2.4 to 8 mhz f x = 2.4 to 4.8 mhz instruction execution time 16 m s (f x = 4 mhz) carrier frequency f x /8, f x /16, f x /64, f x /96, f x /128, f x /192, no carrier (high level) timer 9-bit programmable timer: 1 channel poc circuit on chip supply voltage v dd = 2.0 to 3.6 v v dd = 2.2 to 3.6 v operating ambient temperature t a = e40 to +85 c package 20-pin plastic ssop (7.62 mm (300)) m pd64a m pd65 m pd6p5 2026 10 bits k i0 to k i3 k i/o0 to k i/o7 s 0 , s 1 /led, s 2 port k i port k i/o port s 4 8 3 4 8 3 rom ram system control carrier generator 9-bit timer cpu core x in x out v dd gnd rem s 1 /led
4 m pd64a, 65 data sheet u14380ej3v0ds00 contents 1. pin functions ................................................................................................................ ............... 6 1.1 list of pin functions ....................................................................................................... ........................ 6 1.2 pin i/o circuits............................................................................................................ ............................. 7 1.3 recommended connection of unused pins ....................................................................................... .. 8 2. internal cpu functions ....................................................................................................... ... 9 2.1 program counter (pc) ........................................................................................................ .................... 9 2.2 stack pointer (sp) .......................................................................................................... ......................... 9 2.3 address stack register (asr (rf)) ........................................................................................... ............ 9 2.4 program memory (rom) ........................................................................................................ ................. 10 2.5 data memory (ram) ........................................................................................................... ..................... 10 2.6 data pointer (dp) ........................................................................................................... .......................... 11 2.7 accumulator (a) ............................................................................................................. ......................... 11 2.8 arithmetic and logic unit (alu) ............................................................................................. ............... 12 2.9 flags ....................................................................................................................... .................................. 12 2.9.1 status flag (f) ........................................................................................................... .................... 12 2.9.2 carry flag (cy) ........................................................................................................... .................. 13 3. port registers (px) .......................................................................................................... ......... 14 3.1 k i/o port (p0) ..................................................................................................................... ........................ 15 3.2 k i port/special port (p1) ........................................................................................................ ................. 16 3.2.1 k i port (p 11 : bits 4 to 7 of p1) ....................................................................................................... 16 3.2.2 s 0 port (bit 2 of p1) ............................................................................................................ ........... 16 3.2.3 s 1 /led port (bit 3 of p1) ........................................................................................................ ....... 16 3.2.4 s 2 port (bit 1 of p1) ............................................................................................................ ........... 17 3.3 control register 0 (p3) ..................................................................................................... ...................... 17 3.4 control register 1 (p4) ..................................................................................................... ...................... 18 4. timer ........................................................................................................................ ....................... 19 4.1 timer configuration ......................................................................................................... ....................... 19 4.2 timer operation ............................................................................................................. .......................... 20 4.3 carrier output .............................................................................................................. ............................ 21 4.4 software control of timer output ............................................................................................ ............. 21 5. standby function ............................................................................................................. ......... 22 5.1 outline of standby function ................................................................................................. ................. 22 5.2 standby mode setting and release ............................................................................................ .......... 23 5.3 standby mode release timing ................................................................................................. ............. 25 6. reset ........................................................................................................................ ....................... 26 7. poc circuit .................................................................................................................. ................. 27 7.1 functions of poc circuit .................................................................................................... .................... 28 7.2 oscillation check at low supply voltage ..................................................................................... ........ 28 8. system clock oscillator ...................................................................................................... 29
5 m pd64a, 65 data sheet u14380ej3v0ds00 9. instruction set .............................................................................................................. ............ 30 9.1 machine language output by assembler ........................................................................................ ..... 30 9.2 circuit symbol description .................................................................................................. .................. 31 9.3 mnemonic to/from machine language (assembler output) contrast table ..................................... 32 9.4 accumulator operation instructions .......................................................................................... ........... 36 9.5 i/o instructions ............................................................................................................ ............................ 39 9.6 data transfer instructions .................................................................................................. .................... 40 9.7 branch instructions ......................................................................................................... ....................... 42 9.8 subroutine instructions ..................................................................................................... ..................... 43 9.9 timer operation instructions ................................................................................................ ................. 44 9.10 other instructions ......................................................................................................... .......................... 45 10. assembler reserved words ................................................................................................ 47 10.1 mask option quasi directives ............................................................................................... ................ 47 10.1.1 option and endop quasi directives ........................................................................................ .47 10.1.2 mask option definition quasi directive ................................................................................... ....... 47 11. electrical specifications ................................................................................................... .. 48 12. characteristic curves (reference values) ................................................................. 52 13. application circuit example ................................................................................................ 5 3 14. package drawing ............................................................................................................. ......... 54 15. recommended soldering conditions ................................................................................ 55 appendix a. development tools ............................................................................................... 56 appendix b. functional comparison between m pd64a, 65 and other products .... 57 appendix c. example of remote-control transmission format ................................ 58
6 m pd64a, 65 data sheet u14380ej3v0ds00 1. pin functions 1.1 list of pin functions pin no. symbol function output format after reset 1k i/o0 to k i/o7 cmos high-level output 2 push-pull note 1 15 to 20 3s 0 ? high impedance (off mode) 4s 1 /led cmos push-pull high-level output (led) 5 rem cmos push-pull low-level output 6v dd ?? 7x out ? low level 8x in (oscillation stopped) 9 gnd ?? 10 s 2 ? input (high impedance, stop mode release cannot be used) 11 to 14 k i0 to k i3 note 2 ? input (low level) notes 1. be aware that the drive capability of the low-level output side is held low. 2. in order to prevent malfunction, do not input a high level to all the k i0 to k i3 pins when poc is released due to supply voltage startup (these pins can be left open. when leaving open, keep pull-down resistors connected). 8-bit i/o port. i/o can be switched in 8-bit units. in input mode, a pull-down resistor is added. in output mode, these pins can be used as key scan outputs from the key matrix. input port. can also be used as a key return input from key matrix. in input mode, use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. if input mode is canceled by software, this pin is placed in the off mode and enters a high-impedance state. i/o port. in input mode (s 1 ), this pin can also be used as a key return input from key matrix. use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. in output mode (led), this pin becomes the remote control transmission display output (active low). when the remote control carrier is output from the rem output, this pin outputs a low level from the led output synchronously with the rem signal. infrared remote control transmission output. the output is active high. carrier frequency: f x /8, f x /64, f x /96, high-level, f x /16, f x /128, f x /192 (usable on software) power supply connecting ceramic resonators for system clock. ground. input port. the use of a stop mode release for the s 2 port can be specified by software. when using this pin as a key input from a key matrix, enable the use of the stop mode release (at this time, a pull-down resistor is connected internally.) when the stop mode release is disabled, this pin can be used as an input port that does not release the stop mode even if the release condition is established (at this time, a pull-down resistor is not connected inter- nally.) 4-bit input port. these pins can be used as key return inputs from the key matrix. use of a pull-down resistor can be specified by software in 4-bit units.
7 m pd64a, 65 data sheet u14380ej3v0ds00 1.2 pin i/o circuits the i/o circuits of the m pd64a and 65 pins are shown in partially simplified forms below. (1) k i/o0 to k i/o7 (4) s 0 (5) s 1 /led note the drive capability is held low. (2) k i0 to k i3 (3) rem (6) s 2 p-ch n-ch note n-ch v dd output latch input buffer data output disable selector n-ch input buffer pull-down flag standby release p-ch n-ch v dd output latch carrier generator data off mode pull-down flag n-ch standby release input buffer p-ch n-ch n-ch v dd rem output latch input buffer output disable pull-down flag standby release n-ch input buffer stop release on/off standby release
8 m pd64a, 65 data sheet u14380ej3v0ds00 1.3 recommended connection of unused pins the following connections are recommended for unused pins. table 1-1. recommended connection of unused pins pin connection inside microcontroller outside microcontroller k i/o input mode ? leave open output mode high-level output rem ? s 1 /led output mode (led) setting s 0 off mode setting directly connect to gnd s 2 ? k i ? caution the i/o mode and the pin output level are recommended to be fixed by setting them repeatedly in each loop of the program.
9 m pd64a, 65 data sheet u14380ej3v0ds00 2. internal cpu functions 2.1 program counter (pc): 11 bits this is a binary counter that holds the address information of the program memory. figure 2-1. program counter configuration the program counter contains the address of the instruction that should be executed next. normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. however, when executing jump instructions (jmp, jc, jnc, jf, jnf), the program counter contains the jump destination address written in the operand. when executing the subroutine call instruction (call), the call destination address written in the operand is entered in the pc after the pc contents at the time are saved to the address stack register (asr). if the return instruction (ret) is executed after the call instruction is executed, the address saved to the asr is restored to the pc. after reset, the value of the program counter becomes 000h. 2.2 stack pointer (sp): 1 bit this is a 1-bit register that holds the status of the address stack register. the stack pointer contents are incremented when the call instruction (call) is executed; they are decremented when the return instruction (ret) is executed. after reset, the stack pointer contents are cleared to 0. when the stack pointer overflows (stack level 2 or more) or underflows, the cpu is hung up, causing a system reset signal to be generated and the pc to be cleared to 000h. as no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program. 2.3 address stack register (asr (rf)): 11 bits the address stack register saves the return address of the program after a subroutine call instruction is executed. the lower 8 bits are allocated to the rf of the data memory as a dual-function ram. the register holds the asr value even after the ret is executed. after reset, it holds the previous data (undefined when turning on the power). caution if the rf is accessed as the data memory, the higher 3 bits of the asr become undefined. figure 2-2. address stack register configuration pc9 pc10 pc0 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc asr10 asr9 asr8 asr7 asr6 asr5 asr4 asr3 asr2 asr1 asr0 asr rf
10 m pd64a, 65 data sheet u14380ej3v0ds00 2.4 program memory (rom): 1002 steps 10 bits ( m pd64a) 2026 steps 10 bits ( m pd65) the rom consists of 10 bits per step, and is addressed by the program counter. the program memory stores programs and table data, etc. the 22 steps from 7eah to 7ffh cannot be used in the test program area. figure 2-3. program memory map note the unmounted area and test program area are designed so that a program or data placed in either of them by mistake is returned to the 000h address. 2.5 data memory (ram): 32 4 bits the data memory, which is a static ram consisting of 32 4 bits, is used to hold processed data. the data memory is sometimes processed in 8-bit units. r0 can be used as the rom data pointer. rf is also used as the asr. after reset, r0 is cleared to 00h and r1 to rf hold the previous data (undefined when turning on the power). 10 bits page 0 000h 3ffh 400h 7e9h 7eah 7ffh 000h 3e9h 3eah 7e9h 7eah 7ffh unmounted area note test program area note test program area note page 0 page 1 10 bits (a) pd64a (b) pd65 mm
11 m pd64a, 65 data sheet u14380ej3v0ds00 figure 2-4. data memory configuration 2.6 data pointer (dp): 11 bits the rom data table can be referenced by setting the rom address in the data pointer to call the rom contents. the lower 8 bits of the rom address are specified by r0 of the data memory; and the higher 3 bits by bits 4, 5, and 6 of the p3 register (cr0). after reset, the pointer contents become 000h. figure 2-5. data pointer configuration note set dp 10 of the m pd64a to 0. 2.7 accumulator (a): 4 bits the accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations. after reset, the accumulator contents are left undefined. figure 2-6. accumulator configuration a 3 a 2 a 1 a 0 a r 00 dp 9 dp 8 dp 7 dp 6 dp 5 dp 4 dp 3 dp 2 dp 1 dp 0 r 10 r0 b 4 b 5 p3 register p3 dp 10 b 6 note r 1n (higher 4 bits) r 0n (lower 4 bits) r0 dp (refer to 2.6 data pointer (dp) ) r 10 r 00 r 11 r 01 r 12 r 02 r 13 r 03 r 14 r 04 r 15 r 05 r 16 r 06 r 17 r 07 r 18 r 08 r 19 r 09 r 1a r 0a r 1b r 0b r 1c r 0c r 1d r 0d r 1e r 0e r 1f r 0f r1 r2 r3 r4 r5 r6 r7 r8 r9 ra rb rc rd re rf asr (refer to 2.3 address stack register (asr (rf)) )
12 m pd64a, 65 data sheet u14380ej3v0ds00 2.8 arithmetic and logic unit (alu): 4 bits the arithmetic and logic unit (alu), which is an arithmetic circuit consisting of 4 bits, executes simple manipulations with priority given to logical operations. 2.9 flags 2.9.1 status flag (f) pin and timer statuses can be checked by executing the stts instruction to check the status flag. the status flag is set (1) in the following cases. if the condition specified with the operand is met when the stts instruction has been executed. when standby mode is released. when the release condition is met at the point of executing the halt instruction. (in this case, the system does not enter standby mode.) conversely, the status flag is cleared (0) in the following cases. if the condition specified with the operand is not met when the stts instruction has been executed. while the status flag is set (1), the halt instruction is executed, but the release condition is not met at the point of executing the halt instruction. (in this case, the system does not enter standby mode.) table 2-1. conditions for status flag (f) to be set by stts instruction operand value of stts instruction condition for status flag (f) to be set b 3 b 2 b 1 b 0 0000 high level is input to at least one of the k i pins. 0 1 1 high level is input to at least one of the k i pins. 1 1 0 high level is input to at least one of the k i pins. 1 0 1 the down counter of the timer is 0. 1 any combination [the following condition is added in addition to the above.] of b 2 , b 1 , and b 0 above high level is input to at least one of the s 0 note 1 , s 1 note 1 , and s 2 note 2 pins. notes 1. the s 0 and s 1 pins must be set to input mode (bit 2 of the p4 register is set to 0 and bit 0 to 1). 2. the use of stop mode release for the s 2 pin must be enabled (bit 3 of the p4 register is set to 1).
13 m pd64a, 65 data sheet u14380ej3v0ds00 2.9.2 carry flag (cy) the carry flag is set (1) in the following cases. if the anl instruction or the xrl instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the operand is 1. if the rl instruction or the rlz instruction is executed when bit 3 of the accumulator is 1. if the inc instruction or the scaf instruction is executed when the value of the accumulator is 0fh. the carry flag is cleared (0) in the following cases. if the anl instruction or the xrl instruction is executed when either bit 3 of the accumulator or bit 3 of the operand (or both) is 0. if the rl instruction or the rlz instruction is executed when bit 3 of the accumulator is 0. if the inc instruction or the scaf instruction is executed when the value of the accumulator is other than 0fh. if the orl instruction is executed. when data is written to the accumulator by the mov instruction or the in instruction.
14 m pd64a, 65 data sheet u14380ej3v0ds00 3. port registers (px) the k i/o port, the k i port, the special ports (s 0 , s 1 /led, s 2 ), and the control registers are treated as port registers. port register values after reset are shown below. figure 3-1. port register configuration note : value based on the k i pin state table 3-1. relationship between ports and read/write port name input mode output mode read write read write k i/o pin state output latch output latch output latch k i pin state ? ? ? s 0 pin state ? note ? s 1 /led pin state ? pin state ? s 2 pin state ? ? ? note when in off mode, 1 is always read. port register p0 k i/o7 p 00 after reset ffh k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 p 10 p1 k i3 p 01 fh note k i2 k i1 k i0 s 1 /led s 0 s 2 1 p 11 p3 (control register 0) 0 p 03 03h dp 10 dp 9 dp 8 tctl cary mod 1 mod 0 p 13 p4 (control register 1) 0 p 04 26h 0 k i pull-down s 0 /s 1 pull-down s 2 stop release s 1 /led mode k i/o mode s 0 mode p 14
15 m pd64a, 65 data sheet u14380ej3v0ds00 3.1 k i/o port (p0) the k i/o port is an 8-bit i/o port for key scan output. input/output mode is set by bit 1 of the p4 register. if a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. if a write instruction is executed, data can be written to the output latch regardless of input or output mode. after reset, the port enters output mode, and the value of the output latch (p0) becomes 1111 1111b. the k i/o port includes a pull-down resistor, which functions in input mode only. caution because during double pressing of a key, a high-level output and a low-level output may conflict with each other at the k i/o port, the low-level output current of the k i/o port is held low. therefore, be careful when using the k i/o port for purposes other than key scan output. the k i/o port is designed so that, even when connected directly to v dd within the normal supply voltage range (v dd = 2.0 to 3.6 v), no problem may occur. table 3-2. k i/o port (p0) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 b 0 to b 7 : when reading: in input mode, state of the k i/o pin is read. in output mode, the k i/o pin?s output latch contents are read. when writing: data is written to the k i/o pin?s output latch regardless of input or output mode.
16 m pd64a, 65 data sheet u14380ej3v0ds00 3.2 k i port/special port (p1) 3.2.1 k i port (p 11 : bits 4 to 7 of p1) the k i port is a 4-bit input port for key entry. the pin state can be read. use of a pull-down resistor for the k i port can be specified in 4-bit units by software using bit 5 of the p4 register. after reset, a pull-down resistor is connected. table 3-3. k i /special port register (p1) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name k i3 k i2 k i1 k i0 s 1 /led s 0 s 2 fixed to 1 b 1 : the state of the s 2 pin is read (read only). b 2 : in input mode, the state of the s 0 pin is read (read only). in off mode, this bit is fixed to 1. b 3 : the state of the s 1 /led pin is read regardless of input/output mode (read only). b 4 to b 7 : the state of the k i pin is read (read only). caution in order to prevent malfunction, do not input a high level to all the k i0 to k i3 pins when poc is released due to supply voltage startup (these pins can be left open. when leaving open, keep pull-down resistors connected). 3.2.2 s 0 port (bit 2 of p1) the s 0 port is an input/off mode port. the pin state can be read by setting this port to input mode with bit 0 of the p4 register. in input mode, use of a pull-down resistor for the s 0 and s 1 /led ports can be specified in 2-bit units by software using bit 4 of the p4 register. if input mode is released (thus set to off mode), the pin becomes high impedance but through current does not flow internally. in off mode, 1 can be read regardless of the pin state. after reset, this port is set to off mode, thus becoming high impedance. 3.2.3 s 1 /led port (bit 3 of p1) the s 1 /led port is an i/o port. bit 2 of the p4 register can be used to set input or output mode. the pin state can be read in both input mode and output mode. in input mode, use of a pull-down resistor for the s 0 and s 1 /led ports can be specified in 2- bit units by software using bit 4 of the p4 register. in output mode, the pull-down resistor is automatically disconnected, and this pin becomes the remote control transmission display pin (refer to 4. timer ). after reset, this port enters output mode, and a high level is output.
17 m pd64a, 65 data sheet u14380ej3v0ds00 3.2.4 s 2 port (bit 1 of p1) the s 2 port is an input port. use of a stop mode release for the s 2 port can be specified by bit 3 of the p4 register. when using this port as a key input from a key matrix, enable the use of the stop mode release (bit 3 of p4 register is set to 1) (at this time, a pull-down resistor is connected internally). when the stop mode release is disabled (bit 3 of p4 register is set to 0), this port can be used as an input port that does not release the stop mode even if the release condition is established (at this time, a pull-down resistor is not connected internally). the state of the pin can be read in both cases. after reset, the pin is set to input mode in which the stop mode release is disabled, and enters a high-impedance state. 3.3 control register 0 (p3) control register 0 consists of 8 bits. the contents that can be controlled are as shown below. after reset, the register becomes 0000 0011b. table 3-4. control register 0 (p3) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name ? dp (data pointer) tctl cary mod 1 mod 0 dp 10 note dp 9 dp 8 set 0 fixed 0 0 0 1/1 on refer to table 3-5 . value 1 to 0 1 1 1 1/2 off after reset 0 0 0 0 0 0 1 1 b 0 , b 1 : these bits specify the carrier frequency and duty ratio of the rem output. b 2 : this bit specifies the availability of the carrier of the frequency specified by b 0 and b 1 . 0 = on (with carrier); 1 = off (without carrier; high level) b 3 : this bit changes the carrier frequency and the timer clock?s frequency division ratio. 0 = 1/1 (carrier frequency: the specified value of b 0 and b 1 ; timer clock: f x /64) 1 = 1/2 (carrier frequency: half of the specified value of b 0 and b 1 ; timer clock: f x /128) table 3-5. timer clock and carrier frequency settings b 3 b 2 b 1 b 0 timer clock carrier frequency (duty ratio) 0000f x /64 f x /8 (duty 1/2) 01 f x /64 (duty 1/2) 10 f x /96 (duty 1/2) 11 f x /96 (duty 1/3) 1 without carrier (high level) 1000f x /128 f x /16 (duty 1/2) 01 f x /128 (duty 1/2) 10 f x /192 (duty 1/2) 11 f x /192 (duty 1/3) 1 without carrier (high level) b 4 , b 5 , b 6 : these bits specify the higher 3 bits (dp 8 , dp 9 and dp 10 ) of rom?s data pointer. note set dp 10 of the m pd64a to 0. remark : don?t care
18 m pd64a, 65 data sheet u14380ej3v0ds00 3.4 control register 1 (p4) control register 1 consists of 8 bits. the contents that can be controlled are as shown below. after reset, the register becomes 0010 0110b. table 3-6. control register 1 (p4) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name ? ? k i s 0 /s 1 s 2 s 1 /led k i/o s 0 pull-down pull-down stop release mode mode mode set 0 fixed fixed off off disabled s 1 in off value 1 to 0 to 0 on on enabled led out in after reset 00100110 b 0 : specifies the input mode of the s 0 port. 0 = off mode (high impedance); 1 = in (input mode). b 1 : specifies the i/o mode of the k i/o port. 0 = in (input mode); 1 = out (output mode). b 2 : specifies the i/o mode of the s 1 /led port. 0 = s 1 (input mode); 1 = led (output mode). b 3 : specifies the use of the stop mode release for the s 2 port (with/without pull-down resistor). 0 = disabled (pull-down unavailable); 1 = enabled (pull-down available). b 4 : specifies the availability of the pull-down resistor for the s 0 /s 1 port input mode. 0 = off (unavailable); 1 = on (available). b 5 : specifies the availability of the pull-down resistor for the k i port. 0 = off (unavailable); 1 = on (available). remark in output mode or in off mode, all the pull-down resistors are automatically disconnected.
19 m pd64a, 65 data sheet u14380ej3v0ds00 4. timer 4.1 timer configuration the timer is the block used for creating a remote control transmission pattern. as shown in figure 4-1, it consists of a 9-bit down counter (t 8 to t 0 ), a flag (t 9 ) to enable the 1-bit timer output, and a zero detector. figure 4-1. timer configuration bit 2 of control register 0 (p3) timer operation end signal (halt # 101b release signal) f x /64 f x /128 selector count clock zero detector carrier synchronous circuit carrier signal s 1 /led rem t1 t 9 t 8 t 7 t 6 t 5 t 4 9-bit down counter bit 3 of control register 0 (p3) t 3 t 2 t 1 t 0 t0 t
20 m pd64a, 65 data sheet u14380ej3v0ds00 4.2 timer operation the timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation instruction. the timer operation instructions for making the timer start operation are shown below. mov t0, a mov t1, a mov t, #data10 mov t, @r0 the down counter is decremented (e1) in the cycle of 64/f x or 128/f x note . if the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. at this time, if the timer is in halt mode (halt # 101b) waiting for the timer to stop operation, the halt mode is released and the instruction following the halt instruction is executed. the output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. the following expression indicates the relationship between the timer?s time and the down counter?s set value. timer time = (set value + 1) 64/f x (or 128/f x note ) note this becomes 128/f x if bit 3 of control register 0 is set (1). by setting the flag (t 9 ) that enables the timer output to 1, the timer can output its operation status from the s 1 / led and rem pins. the rem pin can also output the carrier while the timer is in operation. table 4-1. timer output (when t 9 = 1) s 1 /led pin rem pin timer operating l h (or carrier output note ) timer halted h l note the carrier is output if bit 2 of control register 0 is cleared (0). figure 4-2. timer output (when carrier is not output) timer value: (set value + 1) 64/f x (or 128/f x ) led rem
21 m pd64a, 65 data sheet u14380ej3v0ds00 4.3 carrier output the carrier for remote-controlled transmission can be output from the rem pin by clearing (0) bit 2 of control register 0. as shown in figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues to be output until its next fall and then stops due to the function of the carrier synchronous circuit. when the timer starts operation, however, the high-level width of the first carrier may become shorter than the specified width. figure 4-3. timer output (when carrier is output) timer value: (set value + 1) 64/f x (or 128/f x ) led rem (low-level start) rem (high-level start) note 1 note 2 notes 1. error when the rem output ends: lead by carrier low-level width to lag by carrier high- level width 2. error of carrier high-level width: 0 to carrier high-level width 4.4 software control of timer output the timer output can be controlled by software. as shown in figure 4-4, a pulse with a minimum width of 1 instruction cycle (64/f x ) can be output. figure 4-4. pulse output of 1 instruction cycle width mov t, #0000000000b; low-level output from the rem pin mov t, #1000000000b; high-level output from the rem pin mov t, #0000000000b; low-level output from the rem pin 64/f x led rem
22 m pd64a, 65 data sheet u14380ej3v0ds00 5. standby function 5.1 outline of standby function to reduce current consumption, two types of standby modes, i.e., halt mode and stop mode, are available. in stop mode, the system clock stops oscillation. at this time, the x in and x out pins are fixed at a low level. in halt mode, cpu operation halts, while the system clock continues oscillation. when in halt mode, the timer (including rem output and led output) operates. in either stop mode or halt mode, the statuses of the data memory, accumulator, and port register, etc. immediately before the standby mode is set are retained. therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. table 5-1. statuses in standby mode stop mode halt mode setting instruction halt instruction clock oscillator oscillation stopped oscillation continued cpu operation halted data memory immediately preceding status retained operation accumulator immediately preceding status retained statuses flag f 0 (when 1, the flag does not enter the standby mode.) cy immediately preceding status retained port register immediately preceding status retained timer operation halted operable (the count value is reset to 0) cautions 1. write the nop instruction as the first instruction after stop mode is released. 2. when standby mode is released, the status flag (f) is set (1). 3. if, at the point the standby mode has been set, its release condition is met, then the system does not enter the standby mode. however, the status flag (f) is set (1).
23 m pd64a, 65 data sheet u14380ej3v0ds00 5.2 standby mode setting and release the standby mode is set with the halt #b 3 b 2 b 1 b 0 b instruction for both stop mode and halt mode. for the standby mode to be set, the status flag (f) is required to have been cleared (0). the standby mode is released by the release condition specified with the reset (poc) or the operand of the halt instruction. if the standby mode is released, the status flag (f) is set (1). even when the halt instruction is executed in a state in which the status flag (f) is set (1), the standby mode is not set. if the release condition is not met at this time, the status flag is cleared (0). if the release condition is met, the status flag remains set (1). even in the case when the release condition has already been met at the point that the halt instruction is executed, the standby mode is not set. here, also, the status flag (f) is set (1). caution note that depending on the status of the status flag (f), the halt instruction may not be executed. for example, when setting halt mode after checking the key status with the stts instruction, the system does not enter halt mode as long as the status flag (f) remains set (1), sometimes resulting in an unintended operation. in this case, the intended operation can be realized by executing the stts instruction immediately after setting the timer to clear (0) the status flag. example stts #03h ;to check the k i pin status mov t, #0xxh ;to set the timer stts #05h ;to clear the status flag (during this time, be sure not to execute an instruction that may set the status flag.) halt #05h ;to set halt mode table 5-2. addresses executed after standby mode release release condition address executed after release reset 0 address release condition shown in table 5-3 the address following the halt instruction
24 m pd64a, 65 data sheet u14380ej3v0ds00 table 5-3. standby mode setting (halt #b 3 b 2 b 1 b 0 b) and release conditions operand value of halt instruction setting mode precondition for setting release conditions b 3 b 2 b 1 b 0 0000 stop all k i/o pins are high-level output. high level is input to at least one of k i pins. 0 1 1 stop all k i/o pins are high-level output. high level is input to at least one of k i pins. 1 1 0 stop note 1 the k i/o0 pin is high-level output. high level is input to at least one of k i pins. 1 any combination of stop [the following conditions are added in addition to the above.] b 2 b 1 b 0 above ? high level is input to at least one of s 0 , s 1 and s 2 pins note 2 . 0/1 1 0 1 halt ? when the timer?s down counter is 0 notes 1. when setting halt # 110b, configure a key matrix by using the k i/o0 pin and the k i pin so that an internal reset takes effect at the time of program runaway. 2. at least one of the s 0 , s 1 and s 2 pins (the pin used for releasing the standby) must be specified as follows. s 0 , s 1 pins: input mode (specified by bits 0 and 2 of the p4 register) s 2 pin: use of stop mode release enabled (specified by bit 3 of the p4 register) cautions 1. the internal reset takes effect when the halt instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the halt instruction. 2. if stop mode is set when the timer?s down counter is not 0 (timer operating), the system enters stop mode only after all the 10 bits of the timer?s down counter and the timer output enable flag are cleared to 0. 3. write the nop instruction as the first instruction after stop mode is released.
25 m pd64a, 65 data sheet u14380ej3v0ds00 5.3 standby mode release timing (1) stop mode release timing figure 5-1. stop mode release by release condition caution when a release condition is established in the stop mode, the device is released from the stop mode, and goes into a wait state. at this time, if the release condition is not held, the device goes into stop mode again after the wait time has elapsed. therefore, when releasing the stop mode, it is necessary to hold the release condition longer than the wait time. (2) halt mode release timing figure 5-2. halt mode release by release condition wait (52/f x + a ) halt mode operating mode stop mode oscillation stopped oscillation operating mode oscillation halt instruction (stop mode) standby release signal clock a : oscillation growth time halt mode operating mode oscillation o perating mode halt instruction (halt mode) standby release signal clock
26 m pd64a, 65 data sheet u14380ej3v0ds00 6. reset the system is reset by the following occurrences. when the poc circuit has detected low-power voltage when the operand value is illegal or does not satisfy the precondition when the halt instruction is executed when the accumulator is 0h when the rlz instruction is executed when the stack pointer overflows or underflows table 6-1. hardware statuses after reset hardware reset by internal poc circuit in operation reset by internal poc circuit in reset by other factor note 1 standby mode pc (11 bits) 000h sp (1 bit) 0b data r0 = dp 000h memory r1 to rf undefined previous status retained accumulator (a) undefined status flag (f) 0b carry flag (cy) 0b timer (10 bits) 000h port register p0 ffh p1 11 1b note 2 control register p3 03h p4 26h notes 1. the following resets are available. reset when executing the halt instruction (when the operand value is illegal or does not satisfy the precondition) reset when executing the rlz instruction (when a = 0) reset by stack pointer overflow or underflow 2. value according to the k i or s 2 pin status. in order to prevent malfunction, do not input a high level to all the k i0 to k i3 pins when poc is released due to supply voltage startup (these pins can be left open. when leaving open, keep pull-down resistors connected).
27 m pd64a, 65 data sheet u14380ej3v0ds00 7. poc circuit the poc circuit monitors the power supply voltage and applies an internal reset in the microcontroller when the battery is replaced. cautions 1. there are cases in which the poc circuit cannot detect a low power supply voltage of less than 1 ms. therefore, if the power supply voltage has become low for a period of less than 1 ms, the poc circuit may malfunction because it does not generate an internal reset signal. 2. clock oscillation is stopped by the resonator due to low power supply voltage before the poc circuit generates the internal reset signal. in this case, malfunction may result, for example when the power supply voltage is recovered after the oscillation is stopped. this type of phenomenon takes place because the poc circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. if, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. in most cases, normal operation will be resumed. 3. in order to prevent malfunction, do not input a high level to all the k i0 to k i3 pins when poc is released due to supply voltage startup (these pins can be left open. when leaving open, keep pull-down resistors connected).
28 m pd64a, 65 data sheet u14380ej3v0ds00 7.1 functions of poc circuit the poc circuit has the following functions. generates an internal reset signal when v dd v poc . cancels an internal reset signal when v dd > v poc . here, v dd : power supply voltage, v poc : poc detection voltage. notes 1. in reality, an oscillation stabilization wait time must elapse before the circuit is switched to operating mode. the oscillation stabilization wait time is about 246/f x to 694/f x (about 70 to 190 m s, at f x = 3.64 mhz). 2. for the poc circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the v poc for a period of 1 ms or more. therefore, in reality, there is a time lag of up to 1 ms until the reset takes effect. 3. the poc detection voltage (v poc ) varies between approximately 1.7 to 2.0 v; thus, the reset may be canceled at a power supply voltage smaller than the assured range (v dd = 2.0 to 3.6 v). however, as long as the conditions for operating the poc circuit are met, the actual lowest operating power supply voltage is lower than the poc detection voltage. therefore, no malfunction occurs due to the shortage of power supply voltage. however, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to cautions 3 . in 7. poc circuit ). 7.2 oscillation check at low supply voltage a reliable reset operation can be expected from the poc circuit if it satisfies the condition that the clock can oscillate even at a low power supply voltage (the oscillation start voltage of the resonator being even lower than the poc detection voltage). whether this condition is met or not can be checked by measuring the oscillation status on a product which actually contains a poc circuit, as follows. <1> connect a storage oscilloscope to the x out pin so that the oscillation status can be measured. <2> connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage v dd from 0 v (making sure to avoid v dd > 3.6 v). at first (when v dd < approx. 1.7 v), the x out pin is 0 v regardless of the v dd . however, at the point when v dd reaches the poc detection voltage (v poc = 1.85 v (typ.)), the voltage of the x out pin jumps to about 0.5v dd . maintain this power supply voltage for a while to measure the waveform of the x out pin. if, by any chance, the oscillation start voltage of the resonator is lower than the poc detection voltage, the growing oscillation of the x out pin can be confirmed within several ms after v dd has reached v poc . v dd 3.6 v 2.0 v v poc approx. 1.7 v 0 v internal reset signal reset operating ambient temperature t a = e40 to +85 c clock frequency f x = 2.4 to 8 mhz ? poc detection voltage v poc = 1.85 v (typ.) note 3 ? t operating mode reset note 2 note 1
29 m pd64a, 65 data sheet u14380ej3v0ds00 8. system clock oscillator the system clock oscillator is configured by an oscillator circuit for a ceramic resonator (f x = 2.4 to 8 mhz). figure 8-1. system clock the system clock oscillator stops its oscillation after reset or in stop mode. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as the ground. do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. pd64a, 65 x out x in gnd ceramic resonator m
30 m pd64a, 65 data sheet u14380ej3v0ds00 9. instruction set 9.1 machine language output by assembler the bit length of the machine language of this product is 10 bits per word. however, the machine language output by the assembler is extended to 16 bits per word. as shown in the example below, the extension is made by inserting 3 extended bits (111) in two locations. figure 9-1. example of assembler output (10 bits extended to 16 bits) <1> in the case of anl a, @r0h 1 1 1010 1 0000 1010 1 0000 111 111 extended bits extended bits = faf0 <2> in the case of out p0, #data8 0 0 0110 1 1000 0110 1 1000 111 111 extended bits extended bits = e6f8
31 m pd64a, 65 data sheet u14380ej3v0ds00 9.2 circuit symbol description a: accumulator asr: address stack register addr: program memory address cy: carry flag data4: 4-bit immediate data data8: 8-bit immediate data data10: 10-bit immediate data f: status flag pc: program counter pn: port register pair (n = 0, 1, 3, 4) p0n: port register (lower 4 bits) p1n: port register (higher 4 bits) romn: bit n of the program memory (n = 0 to 9) rn: register pair r0n: data memory (general-purpose register; n = 0 to f) r1n: data memory (general-purpose register; n = 0 to f) sp: stack pointer t: timer register t0: timer register (lower 4 bits) t1: timer register (higher 4 bits) ( ): content addressed with
32 m pd64a, 65 data sheet u14380ej3v0ds00 9.3 mnemonic to/from machine language (assembler output) contrast table accumulator operation instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle anl a, r0n fben (a) ? (a) (rmn) m = 0, 1 n = 0 to f 11 a, r1n faen cy ? a 3 rmn 3 a, @r0h faf0 (a) ? (a) ((p13), (r0)) 7-4 cy ? a 3 rom 7 a, @r0l fbf0 (a) ? (a) ((p13), (r0)) 3-0 cy ? a 3 rom 3 a, #data4 fbf1 data4 (a) ? (a) data4 2 cy ? a 3 data4 3 orl a, r0n fden (a) ? (a) (rmn) m = 0, 1 n = 0 to f 1 a, r1n fcen cy ? 0 a, @r0h fcf0 (a) ? (a) ((p13), (r0)) 7-4 cy ? 0 a, @r0l fdf0 (a) ? (a) ((p13), (r0)) 3-0 cy ? 0 a, #data4 fdf1 data4 (a) ? (a) data4 2 cy ? 0 xrl a, r0n f5en (a) ? (a) (rmn) m = 0, 1 n = 0 to f 1 a, r1n f4en cy ? a 3 rmn 3 a, @r0h f4f0 (a) ? (a) ((p13), (r0)) 7-4 cy ? a 3 rom 7 a, @r0l f5f0 (a) ? (a) ((p13), (r0)) 3-0 cy ? a 3 rom 3 a, #data4 f5f1 data4 (a) ? (a) data4 2 cy ? a 3 data4 3 inc a f4f3 (a) ? (a) + 1 1 if (a) = 0 cy ? 1 else cy ? 0 rl a fcf3 (a n+1 ) ? (a n ), (a 0 ) ? (a 3 ) cy ? a 3 rlz a fef3 if a = 0 reset else (a n+1 ) ? (a n ), (a 0 ) ? (a 3 ) cy ? a 3
33 m pd64a, 65 data sheet u14380ej3v0ds00 input/output instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle in a, p0n fff8 + n ? ? (a) ? (pmn) m = 0, 1 n = 0, 1, 3, 4 1 1 a, p1n fef8 + n ? ? cy ? 0 out p0n, a e5f8 + n ? ? (pmn) ? (a) m = 0, 1 n = 0, 1, 3, 4 p1n, a e4f8 + n ? ? anl a, p0n fbf8 + n ? ? (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n faf8 + n ? ? cy ? a 3 pmn 3 orl a, p0n fdf8 + n ? ? (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n fcf8 + n ? ? cy ? 0 xrl a, p0n f5f8 + n ? ? (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n f4f8 + n ? ? cy ? a 3 pmn 3 mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle out pn, #data8 e6f8 + n data8 (pn) ? data8 n = 0, 1, 3, 4 2 1 remark pn: p1n-p0n are handled in pairs. data transfer instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov a, r0n ffen (a) ? (rmn) m = 0, 1 n = 0 to f 1 1 a, r1n feen cy ? 0 a, @r0h fef0 (a) ? ((p13), (r0)) 7-4 cy ? 0 a, @r0l fff0 (a) ? ((p13), (r0)) 3-0 cy ? 0 a, #data4 fff1 data4 (a) ? data4 2 cy ? 0 r0n, a e5en (rmn) ? (a) m = 0, 1 n = 0 to f 1 r1n, a e4en mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov rn, #data8 e6en data8 ? (r1n-r0n) ? data8 n = 0 to f 2 1 rn, @r0 e7en ? ? (r1n-r0n) ? ((p13), (r0)) n = 1 to f 1 remark rn: r1n-r0n are handled in pairs.
34 m pd64a, 65 data sheet u14380ej3v0ds00 branch instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle jmp addr (page 0) e8f1 addr pc ? addr 2 1 addr (page 1) e9f1 addr jc addr (page 0) ecf1 addr if cy = 1 pc ? addr addr (page 1) eaf1 addr else pc ? pc + 2 jnc addr (page 0) edf1 addr if cy = 0 pc ? addr addr (page 1) ebf1 addr else pc ? pc + 2 jf addr (page 0) eef1 addr if f = 1 pc ? addr addr (page 1) f0f1 addr else pc ? pc + 2 jnf addr (page 0) eff1 addr if f = 0 pc ? addr addr (page 1) f1f1 addr else pc ? pc + 2 caution 0 and 1, which refer to page0 and 1, are not written when describing mnemonics. subroutine instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle call addr (page 0) e6f2 e8f1 addr sp ? sp + 1, asr ? pc, pc ? addr 3 2 addr (page 1) e6f2 e9f1 addr ret e8f2 pc ? asr, sp ? sp e 1 1 1 caution 0 and 1, which refer to page0 and 1, are not written when describing mnemonics. timer operation instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov a, t0 ffff (a) ? (tn) n = 0, 1 1 1 a, t1 feff cy ? 0 t0, a e5ff (tn) ? (a) n = 0, 1 t1, a f4ff (t) n ? 0 mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov t, #data10 e6ff data10 (t) ? data10 1 1 t, @r0 f4ff (t) ? ((p13), (r0))
35 m pd64a, 65 data sheet u14380ej3v0ds00 other instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle halt #data4 e2f1 data4 standby mode 2 1 stts #data4 e3f1 data4 if statuses match f ? 1 else f ? 0 r0n e3en if statuses match f ? 11 else f ? 0 n = 0 to f scaf faf3 if a = 0fh cy ? 1 else cy ? 0 nop e0e0 pc ? pc + 1
36 m pd64a, 65 data sheet u14380ej3v0ds00 9.4 accumulator operation instructions anl a, r0n anl a, r1n <1> instruction code: 1 101r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) ? (a) (rmn) m = 0, 1 n = 0 to f cy ? a 3 rmn 3 the accumulator contents and the register rmn contents are anded and the results are entered in the accumulator. anl a, @r0h anl a, @r0l <1> instruction code: 1 1010/110000 <2> cycle count: 1 <3> function: (a) ? (a) ((p13), (r0)) 7-4 (in the case of anl a, @r0h) cy ? a 3 rom 7 (a) ? (a) ((p13), (r0)) 3-0 (in the case of anl a, @r0l) cy ? a 3 rom 3 the accumulator contents and the program memory contents specified with the control register p13 and register pair r 10 -r 00 are anded and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 , and b 4 take effect. if l is specified, b 3 , b 2 , b 1 , and b 0 take effect. program memory (rom) organization anl a, #data4 <1> instruction code: 1 101110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) ? (a) data4 cy ? a 3 data4 3 the accumulator contents and the immediate data are anded and the results are entered in the accumulator. b 9 b 8 b 7 b 6 h l b 5 valid bits at the time of accumulator operation b 4 b 3 b 2 b 1 b 0
37 m pd64a, 65 data sheet u14380ej3v0ds00 orl a, r0n orl a, r1n <1> instruction code: 1 110r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) ? (a) (rmn) m = 0, 1 n = 0 to f cy ? 0 the accumulator contents and the register rmn contents are ored and the results are entered in the accumulator. orl a, @r0h orl a, @r0l <1> instruction code: 1 1100/110000 <2> cycle count: 1 <3> function: (a) ? (a) (p13), (r0)) 7-4 (in the case of orl a, @r0h) (a) ? (a) (p13), (r0)) 3-0 (in the case of orl a, @r0l) cy ? 0 the accumulator contents and the program memory contents specified with the control register p13 and register pair r 10 -r 00 are ored and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 , and b 4 take effect. if l is specified, b 3 , b 2 , b 1 , and b 0 take effect. orl a, #data4 <1> instruction code: 1 110110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) ? (a) data4 cy ? 0 the accumulator contents and the immediate data are ored and the results are entered in the accumulator. xrl a, r0n xrl a, r1n <1> instruction code: 1 010r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) ? (a) (rmn) m = 0, 1 n = 0 to f cy ? a 3 rmn 3 the accumulator contents and the register rmn contents are exclusive-ored and the results are entered in the accumulator.
38 m pd64a, 65 data sheet u14380ej3v0ds00 xrl a, @r0h xrl a, @r0l <1> instruction code: 1 0100/110000 <2> cycle count: 1 <3> function: (a) ? (a) (p13), (r0)) 7-4 (in the case of xrl a, @r0h) cy ? a 3 rom 7 (a) ? (a) (p13), (r0)) 3-0 (in the case of xrl a, @r0l) cy ? a 3 rom 3 the accumulator contents and the program memory contents specified with the control register p13 and register pair r 10 -r 00 are exclusive-ored and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 , and b 4 take effect. if l is specified, b 3 , b 2 , b 1 , and b 0 take effect. xrl a, #data4 <1> instruction code: 1 010110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) ? (a) data4 cy ? a 3 data4 3 the accumulator contents and the immediate data are exclusive-ored and the results are entered in the accumulator. inc a <1> instruction code: 1 010010011 <2> cycle count: 1 <3> function: (a) ? (a) + 1 if a = 0 cy ? 1 else cy ? 0 the accumulator contents are incremented (+1). rl a <1> instruction code: 1 110010011 <2> cycle count: 1 <3> function: (a n + 1 ) ? (a n ), (a 0 ) ? (a 3 ) cy ? a 3 the accumulator contents are rotated counterclockwise bit by bit. rlz a <1> instruction code: 1 111010011 <2> cycle count: 1 <3> function: if a = 0 reset else (a n + 1 ) ? (a n ), (a 0 ) ? (a 3 ) cy ? a 3 the accumulator contents are rotated counterclockwise bit by bit. if a = 0h at the time of instruction execution, an internal reset takes effect.
39 m pd64a, 65 data sheet u14380ej3v0ds00 9.5 i/o instructions in a, p0n in a, p1n <1> instruction code: 1 111p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) ? (pmn) m = 0, 1 n = 0, 1, 3, 4 cy ? 0 the port pmn data is loaded (read) into the accumulator. out p0n, a out p1n, a <1> instruction code: 0 010p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (pmn) ? (a) m = 0, 1 n = 0, 1, 3, 4 the accumulator contents are transferred to port pmn to be latched. anl a, p0n anl a, p1n <1> instruction code: 1 101p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy ? a 3 pmn the accumulator contents and the port pmn contents are anded and the results are entered in the accumulator. orl a, p0n orl a, p1n <1> instruction code: 1 110p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy ? 0 the accumulator contents and the port pmn contents are ored and the results are entered in the accumulator. xrl a, p0n xrl a, p1n <1> instruction code: 1 010p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) ? (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy ? a 3 pmn the accumulator contents and the port pmn contents are exclusive-ored and the results are entered in the accumulator.
40 m pd64a, 65 data sheet u14380ej3v0ds00 out pn, #data8 <1> instruction code: 0 011011p 2 p 1 p 0 0d 7 d 6 d 5 d 4 0d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (pn) ? data8 n = 0, 1, 3, 4 the immediate data is transferred to port pn. in this case, port pn refers to p 1n -p 0n operating in pairs. 9.6 data transfer instructions mov a, r0n mov a, r1n <1> instruction code: 1 111r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) ? (rmn) m = 0, 1 n = 0 to f cy ? 0 the register rmn contents are transferred to the accumulator. mov a, @r0h <1> instruction code: 1 111010000 <2> cycle count: 1 <3> function: (a) ? ((p13), (r0)) 7-4 cy ? 0 the higher 4 bits (b 7 b 6 b 5 b 4 ) of the program memory specified with control register p13 and register pair r 10 -r 00 are transferred to the accumulator. b 9 is ignored. mov a, @r0l <1> instruction code: 1 111110000 <2> cycle count: 1 <3> function: (a) ? ((p13), (r0)) 3-0 cy ? 0 the lower 4 bits (b 3 b 2 b 1 b 0 ) of the program memory specified with control register p13 and register pair r 10 -r 00 are transferred to the accumulator. b 8 is ignored. program memory (rom) contents b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 @r 0 h@r 0 l mov a, #data4 <1> instruction code: 1 111110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) ? data4 cy ? 0 the immediate data is transferred to the accumulator.
41 m pd64a, 65 data sheet u14380ej3v0ds00 mov r0n, a mov r1n, a <1> instruction code: 0 010r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (rmn) ? (a) m = 0, 1 n = 0 to f the accumulator contents are transferred to register rmn. mov rn, #data8 <1> instruction code: 0 01100r 3 r 2 r 1 r 0 0d 7 d 6 d 5 d 4 0d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (r1n-r0n) ? data8 n = 0 to f the immediate data is transferred to the register. using this instruction, registers operate as register pairs. the pair combinations are as follows. r 0 : r 10 - r 00 r 1 : r 11 - r 01 r e : r 1e - r 0e r f : r 1f - r 0f lower column higher column mov rn, @r0 <1> instruction code: 0 01110r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (r1n-r0n) ? ((p13), r0)) n = 1 to f the program memory contents specified with control register p13 and register pair r 10 -r 00 are transferred to register pair r1n-r0n. the program memory consists of 10 bits and has the following state after the transfer to the register. b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 @r0 ? r1n r0n program memory the higher 3 bits of the program memory address is specified with the control register (p13). ?
42 m pd64a, 65 data sheet u14380ej3v0ds00 9.7 branch instructions the program memory consists of pages in steps of 1k (000h to 3ffh). however, as the assembler automatically performs page optimization, it is unnecessary to designate pages. the pages allowed for each product are as follows. m pd64a (rom: 1k steps): page 0 m pd65 (rom: 2k steps): pages 0, 1 m pd6p5 (prom: 2k steps): pages 0, 1 jmp addr <1> instruction code: page 0 010001000 1 , page 1 0100110001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: pc ? addr the 10 bits (pc 9-0 ) of the program counter are replaced directly by the specified address addr (a 9 to a 0 ). jc addr <1> instruction code: page 0 011001000 1 , page 1 0101010001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if cy = 1 pc ? addr else pc ? pc + 2 if the carry flag cy is set (1), a jump is made to the address specified with addr (a 9 to a 0 ). jnc addr <1> instruction code: page 0 011011000 1 , page 1 0101110001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if cy = 0 pc ? addr else pc ? pc + 2 if the carry flag cy is cleared (0), a jump is made to the address specified with addr (a 9 to a 0 ). jf addr <1> instruction code: page 0 011101000 1 , page 1 1000010001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if f = 1 pc ? addr else pc ? pc + 2 if the status flag f is set (1), a jump is made to the address specified with addr (a 9 to a 0 ). jnf addr <1> instruction code: page 0 011111000 1 , page 1 1000110001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if f = 0 pc ? addr else pc ? pc + 2 if the status flag f is cleared (0), a jump is made to the address specified with addr (a 9 to a 0 ).
43 m pd64a, 65 data sheet u14380ej3v0ds00 9.8 subroutine instructions the program memory consists of pages in steps of 1k (000h to 3ffh). however, as the assembler automatically performs page optimization, it is unnecessary to designate pages. the pages allowed for each product are as follows. m pd64a (rom: 1k steps): page 0 m pd65 (rom: 2k steps): pages 0, 1 m pd6p5 (prom: 2k steps): pages 0, 1 call addr <1> instruction code: 0 011010010 page 0 010001000 1 , page 1 0100110001 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 2 <3> function: sp ? sp + 1 asr ? pc pc ? addr the stack pointer value is incremented (+1) and the program counter value is saved to the address stack register. the address specified with the operand addr (a 9 to a 0 ) is then entered in the program counter. if a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. ret <1> instruction code: 0 100010010 <2> cycle count: 1 <3> function: pc ? asr sp ? sp e 1 the value saved in the address stack register is restored to the program counter. the stack pointer is then decremented (e1). if a borrow is generated when the stack pointer value is decremented (e1), an internal reset takes effect.
44 m pd64a, 65 data sheet u14380ej3v0ds00 9.9 timer operation instructions mov a, t0 mov a, t1 <1> instruction code: 1 1110/111111 <2> cycle count: 1 <3> function: (a) ? (tn) n = 0, 1 cy ? 0 the timer tn contents are transferred to the accumulator. t1 corresponds to (t 9 , t 8 , t 7 , t 6 ); t0 corresponds to (t 5 , t 4 , t 3 , t 2 ). t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 can be set with t1 t0 mov t, #data10 mov t, @r0 t mov t0, a mov t1, a <1> instruction code: 0 0100/111111 <2> cycle count: 1 <3> function: (tn) ? (a) n = 0, 1 the accumulator contents are transferred to timer register tn. t1 corresponds to (t 9 , t 8 , t 7 , t 6 ); t0 corresponds to (t 5 , t 4 , t 3 , t 2 ). after executing this instruction, if data is transferred to t1, t 1 becomes 0; if data is transferred to t0, t 0 becomes 0. mov t, #data10 <1> instruction code: 0 011011111 t 1 t 9 t 8 t 7 t 6 t 0 t 5 t 4 t 3 t 2 <2> cycle count: 1 <3> function: (t) ? data10 the immediate data is transferred to timer register t (t 9 -t 0 ). remark the timer time is set with (set value + 1) 64/f x (or 128/f x ).
45 m pd64a, 65 data sheet u14380ej3v0ds00 mov t, @r0 <1> instruction code: 0 011111111 <2> cycle count: 1 <3> function: (t) ? ((p13), (r0)) the program memory contents specified by the control register p13 and the register pair r 10 -r 00 are transferred to timer register t (t 9 to t 0 ). the program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t1 t0 t 1 t 0 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 @r 0 ? program memory timer t the higher 3 bits of the program memory address are specified by the control register (p13). caution when setting a timer value in the program memory, be sure to use the dt quasi directive. 9.10 other instructions halt #data4 <1> instruction code: 0 001010001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: standby mode places the cpu in standby mode. the condition to cancel the standby mode (halt/stop mode) is specified by the immediate data. stts r0n <1> instruction code: 0 00110r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: if statuses match f ? 1 else f ? 0 n = 0 to f the s 0 , s 1 , k i/o , k i , and timer statuses are compared with the register r 0n contents. if at least one of the statuses matches the bits that have been set, status flag f is set (1). if none of them match, status flag f is cleared (0).
46 m pd64a, 65 data sheet u14380ej3v0ds00 stts #data4 <1> instruction code: 0 001110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: if statuses match f ? 1 else f ? 0 the s 0 , s 1 , k i/o , k i , and timer statuses are compared with the immediate data contents. if at least one of the statuses matches the bits that have been set, status flag f is set (1). if none of them match, status flag f is cleared (0). scaf (set carry if a cc = f h ) <1> instruction code: 1 101010011 <2> cycle count: 1 <3> function: if a = 0fh cy ? 1 else cy ? 0 the carry flag cy is set (1) if the accumulator contents are f h . the accumulator values after executing the scaf instruction are as follows. accumulator value carry flag before execution after execution 0 0000 0 (clear) 01 0001 0 (clear) 011 0011 0 (clear) 0111 0111 0 (clear) 1111 1111 1 (set) remark : don?t care nop <1> instruction code: 0 000000000 <2> cycle count: 1 <3> function: pc ? pc + 1 no operation
47 m pd64a, 65 data sheet u14380ej3v0ds00 10. assembler reserved words 10.1 mask option quasi directives when creating the m pd64a and 65 program, it is necessary to use a mask option quasi directive in the assembler?s source program. 10.1.1 option and endop quasi directives the option and subsequent quasi directives down to the endop quasi directive are called the mask option definition block. the format of the mask option definition block is as follows. format symbol field mnemonic field operand field comment field [label:] option [; comment] : : endop 10.1.2 mask option definition quasi directive the quasi directive that can be used in the mask option definition block is shown in table 10-1. the mask option definition can only be specified as follows. be sure to specify the following quasi directive. example symbol field mnemonic field operand field comment field option usepoc ; poc circuit incorporated endop table 10-1. mask option definition quasi directive name mask option definition quasi directive pro file address value data value poc usepoc 2044h 01 (poc circuit incorporated)
48 m pd64a, 65 data sheet u14380ej3v0ds00 11. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol conditions ratings unit power supply voltage v dd e0.3 to +3.8 v input voltage v i k i/o , k i , s 0 , s 1 , s 2 e0.3 to v dd + 0.3 v output voltage v o e0.3 to v dd + 0.3 v output current, high i oh note rem peak value e30 ma rms value e20 ma led peak value e7.5 ma rms value e5 ma per k i/o pin peak value e13.5 ma rms value e9 ma total of led and k i/o pins peak value e18 ma rms value e12 ma output current, low i ol note rem peak value 7.5 ma rms value 5 ma led peak value 7.5 ma rms value 5 ma operating ambient t a e40 to +85 c temperature storage temperature t stg e65 to +150 c note the rms value should be calculated as follows: [rms value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended power supply voltage range (t a = e40 to +85 c) parameter symbol conditions min. typ. max. unit power supply voltage v dd f x = 2.4 to 8 mhz 2.0 3.0 3.6 v ?
49 m pd64a, 65 data sheet u14380ej3v0ds00 dc characteristics (t a = e40 to +85 c, v dd = 2.0 to 3.6 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 s 2 0.8v dd v dd v v ih2 k i/o 0.7v dd v dd v v ih3 k i , s 0 , s 1 0.65v dd v dd v input voltage, low v il1 s 2 0 0.2v dd v v il2 k i/o 0 0.3v dd v v il3 k i , s 0 , s 1 0 0.15v dd v input leakage i lih1 k i 3 m a current, high v i = v dd , pull-down resistor not incorporated i lih2 s 0 , s 1 , s 2 3 m a v i = v dd , pull-down resistor not incorporated input leakage i lil1 k i v i = 0 v e3 m a current, low i lil2 k i/o v i = 0 v e3 m a i lil3 s 0 , s 1 , s 2 v i = 0 v e3 m a output voltage, high v oh1 rem, led, k i/o i oh = e0.3 ma 0.8v dd v output voltage, low v ol1 rem, led i ol = 0.3 ma 0.3 v v ol2 k i/o i ol = 15 m a 0.4 v output current, high i oh1 rem v dd = 3.0 v, v oh = 1.0 v e5 e12 ma i oh2 k i/o v dd = 3.0 v, v oh = 2.2 v e2.5 e7 ma output current, low i ol1 k i/o v dd = 3.0 v, v ol = 0.4 v 30 70 m a v dd = 3.0 v, v ol = 2.2 v 100 390 m a on-chip pull-down r 1 k i , s 0 , s 1 , s 2 75 150 300 k w resistor r 2 k i/o 130 250 500 k w data retention power v dddr in stop mode 0.9 3.6 v supply voltage supply current i dd1 operating f x = 8.0 mhz, v dd = 3 v 10% 0.8 1.6 ma mode f x = 4.0 mhz, v dd = 3 v 10% 0.7 1.4 ma i dd2 halt mode f x = 8.0 mhz, v dd = 3 v 10% 0.75 1.5 ma f x = 4.0 mhz, v dd = 3 v 10% 0.65 1.3 ma i dd3 stop mode v dd = 3 v 10% 1.9 9.0 m a v dd = 3 v 10%, t a = 25 c 1.9 5.0 m a
50 m pd64a, 65 data sheet u14380ej3v0ds00 ac characteristics (t a = e40 to +85 c, v dd = 2.0 to 3.6 v) parameter symbol conditions min. typ. max. unit instruction execution time t cy 7.9 27 m s k i , s 0 , s 1 , s 2 high-level t h 10 m s width when standby mode is released in halt mode 10 m s in stop mode note m s note 10 + 52/f x + oscillation growth time remark t cy = 64/f x (f x : system clock oscillation frequency) poc circuit (t a = e40 to +85 c) parameter symbol conditions min. typ. max. unit poc detection voltage note v poc 1.85 2.0 v note the voltage with which the poc circuit cancels an internal reset. if v poc < v dd , the internal reset is canceled. from the time of v poc 3 v dd until the internal reset takes effect, a lag of up to 1 ms occurs. when the period of v poc 3 v dd lasts less than 1 ms, the internal reset may not take effect. system clock oscillator characteristics (t a = e40 to +85 c, v dd = 2.0 to 3.6 v) parameter symbol conditions min. typ. max. unit oscillation frequency f x 2.4 3.64 8.0 mhz (ceramic resonator)
51 m pd64a, 65 data sheet u14380ej3v0ds00 recommended ceramic resonator (t a = e40 to +85 c) manufacturer frequency recommended constant part number (mhz) remark c1 [pf] c2 [pf] min. max. tdk corp. fcr3.52mc5 3.52 2.0 3.6 fcr3.58mc5 3.58 fcr3.64mc5 3.64 fcr3.84mc5 3.84 fcr4.0mc5 4.0 fcr6.0mc5 6.0 fcr8.0mc5 8.0 murata mfg. co., ltd csa2.50mg040 2.5 100 100 cst2.50mg040 csa3.52mg 3.52 30 30 cst3.52mgw csts0352mg03 csa3.58mg 3.58 30 30 cst3.58mgw cst0358mg03 csa3.64mg 3.64 30 30 cst3.64mgw csts0364mg03 csa3.84mg 3.84 30 30 cst3.84mgw cst0384mg03 csa4.00mg 4.0 30 30 cst4.00mgw csts0400mg03 csa6.00mg 6.0 30 30 cst6.00mgw csts0600mg03 csa8.00mtz 8.0 30 30 cst8.00mtw csts0800mg03 external circuit example unnecessary (on-chip c type) power supply voltage [v] unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) unnecessary (on-chip c type) x in x out c1 c2
52 m pd64a, 65 data sheet u14380ej3v0ds00 12. characteristic curves (reference values) - 20 - 18 - 16 - 14 - 12 - 10 - 8 - 6 - 4 - 2 0 v dd v dd - 1v dd - 2v dd - 3 high-level output current i oh [ma] high-level output voltage v oh [v] i oh vs. v oh (rem, led, k i/o ) (t a = 25 c, v dd = 3.0 v) power supply current i dd [ma] power suppl y volta g e v dd [ v ] i dd vs. v dd (f x = 4 mhz) (t a = 25 c) 1.5 2 3 2.5 3.6 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 operating mode halt mode 1.5 2 3 2.5 3.6 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 power supply current i dd [ma] power supply volta g e v dd [v] i dd vs. v dd (f x = 8 mhz) (t a = 25 c) operating mode halt mode 25 20 15 10 5 0 12 3 low-level output current i ol [ma] low-level output volta g e v ol [v] i ol vs. v ol (rem, led) (t a = 25 c, v dd = 3.0 v) 500 450 400 350 300 250 200 150 100 50 0123 low-level output current i ol [ a] m low-level output voltage v ol [v] i ol vs. v ol (k i/o ) (t a = 25 c, v dd = 3.0 v)
53 m pd64a, 65 data sheet u14380ej3v0ds00 13. application circuit example example of application to system remote-control transmitter (48 keys; mode selection switch accommodated) note s 2 : set this pin to disabled when releasing stop mode. remote-control transmitter (56 keys accommodated) k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 note k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 6 = 48 keys + mode selection switch k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 7 = 56 keys +
54 m pd64a, 65 data sheet u14380ej3v0ds00 14. package drawing remark the external dimensions and material of the es version are the same as those of the mass-produced version. ns c dm m p l u t g f e b k j detail of lead end s 20 11 110 a h i item b c i l m n 20-pin plastic ssop (7.62 mm (300)) a k d e f g h j p t millimeters 0.65 (t.p.) 0.475 max. 0.13 0.5 6.1 0.2 0.10 6.65 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 - 0.07 1.0 0.2 3 + 5 - 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s20mc-65-5a4-2
55 m pd64a, 65 data sheet u14380ej3v0ds00 15. recommended soldering conditions the m pd64a and 65 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representa- tive. table 15-1. surface mounting type soldering conditions m pd64amc- -5a4: 20-pin plastic ssop (7.62 mm (300)) m pd65mc- -5a4: 20-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c or higher), ir35-00-3 count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. (200 c or higher), vp15-00-3 count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max, count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together (except for partial heating).
56 m pd64a, 65 data sheet u14380ej3v0ds00 appendix a. development tools emulators are provided for the m pd64a and 65 emulation tools. hardware emulators (eb-65, eb-69 note ) these are tools used to emulate the m pd64a and 65. note products of naito densei machida mfg. co., ltd. for details, consult naito densei machida mfg. co., ltd. (+81-44-822-3813). software assembler (as6133) this is a development tool for remote control transmitter software. part number list of as6133 host machine os supply medium part number pc-9800 series ms-dos ? (ver. 5.0 to ver. 6.2) 3.5-inch 2hd m s5a13as6133 (cpu: 80386 or more) ibm pc/at ? compatible ms-dos (ver. 6.0 to ver. 6.22) 3.5-inch 2hc m s7b13as6133 pc dos ? (ver. 6.1 to ver. 6.3) caution although ver.5.0 or later has a task swap function, this function cannot be used with this software.
57 m pd64a, 65 data sheet u14380ej3v0ds00 item m pd62 m pd62a m pd64 m pd64a m pd65 rom capacity 512 10 bits 512 10 bits 1002 10 bits 1002 10 bits 2026 10 bits ram capacity 32 4 bits stack 1 level (multiplexed with rf of ram) key matrix 8 6 = 48 keys 8 7 = 56 keys key extended input s 0 , s 1 s 0 , s 1 , s 2 clock frequency ceramic oscillation ceramic oscillation ceramic oscillation ceramic oscillation f x = 2.4 to 8 mhz f x = 2.4 to 8 mhz f x = 2.4 to 8 mhz f x = 2.4 to 8 mhz f x = 2.4 to 4 mhz f x = 2.4 to 4 mhz (with poc circuit) (with poc circuit) timer clock f x /64, f x /128 count start writing count value carrier frequency f x /8, f x /64, f x /96 (timer clock: f x /64) f x /16, f x /128, f x /192 (timer clock: f x /128) no carrier output start synchronized with timer instruction execution time 16 m s (f x = 4 mhz) mov rn, @r0 instruction n = 1 to f standby mode reset reset input, poc poc release halt mode for timer only. condition stop mode for only releasing k i (halt (k i/o high-level output or k i/o0 high-level output) instruction) relationship between halt halt instruction not executed when f = 1 instruction execution and status flag (f) poc circuit mask option provided low level output to reset pin on detection generates internal reset signal on detection poc detection v poc = 1.6 v (typ.) v poc = 1.85 v (typ.) v poc = 1.6 v (typ.) v poc = 1.85 v (typ.) voltage mask option poc circuit only none supply voltage v dd = 1.8 to 3.6 v v dd = 2.0 to 3.6 v v dd = 1.8 to 3.6 v v dd = 2.0 to 3.6 v v dd = 2.2 to 3.6 v v dd = 2.2 to 3.6 v (with poc circuit) (with poc circuit) operating ambient t a = e40 to +85 c t a = e40 to +85 c t a = e40 to +85 c t a = e40 to +85 c temperature t a = e20 to +70 c t a = e20 to +70 c (with poc circuit) (with poc circuit) electrical specifications, refer to the data sheet for each product. recommended soldering conditions package 20-pin plastic ssop 20-pin plastic 20-pin plastic ssop sop 20-pin plastic ssop one-time prom version m pd6p4b m pd6p5 appendix b. functional comparison between m pd64a, 65 and other products
58 m pd64a, 65 data sheet u14380ej3v0ds00 appendix c. example of remote-control transmission format (in the case of nec transmission format in one-shot command transmission mode) caution when using the nec transmission format, please apply for a custom code at nec. (1) rem output waveform (from <2> on, the output is made only when the key is kept pressed) rem output 58.5 to 76.5 ms 108 ms 108 ms <1> <2> remark if the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (led) can be reduced by sending the reader code and the stop bit from the second time. (2) enlarged waveform of <1> rem output 13.5 ms leader code 9 ms 4.5 ms custom code 8 bits custom code , 8 bits data code 8 bits data code 8 bits 27 ms 18 to 36 ms 58.5 to 76.5 ms stop bit 1 bit <3> (3) enlarged waveform of <3> rem output 9 ms 13.5 ms 0 4.5 ms 1100 2.25 ms 1.125 ms 0.56 ms (4) enlarged waveform of <2> rem output 9 ms 11.25 ms 2.25 ms 0.56 ms stop bit leader code
59 m pd64a, 65 data sheet u14380ej3v0ds00 (5) carrier waveform (enlarged waveform of each code?s high period) rem output 8.77 s 9 ms or 0.56 ms carrier frequency: 38 khz 26.3 s m m (6) bit array of each code c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 ' c 0 or c o c 1 ' c 1 or c 1 c 2 ' c 2 or c 2 c 3 ' c 3 or c 3 c 4 ' c 4 or c 4 c 5 ' c 5 or c 5 c 6 ' c 6 or c 6 c 7 ' c 7 or c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 = = = = = = = = data code data code custom code , custom code leader code caution to prevent malfunction with other systems when receiving data in the nec transmission format, the total 32 bits of the 16-bit custom codes (custom code, custom code?) and the 16-bit data codes (data code, data code) must not only be fully decoded (make sure to check data code as well) but also checked to make sure that no signals are present.
60 m pd64a, 65 data sheet u14380ej3v0ds00 [memo]
61 m pd64a, 65 data sheet u14380ej3v0ds00 [memo]
62 m pd64a, 65 data sheet u14380ej3v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
63 m pd64a, 65 data sheet u14380ej3v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd64a, 65 ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. m8e 00. 4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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